Recently, the need for a high transfer speed between LSIs (large Scale Integrated circuits) has increased more and more along with improvements in the performance of semi-conductor devices such as CPUs (Central Processing Units), chip sets, and the like. Naturally, a high transfer speed between LSIs greatly affects the performance of a computer system on which the LSIs are mounted.
In high-speed transmission between LSIs, each design element affecting a signal waveform transmitted between LSIs requires high design accuracy in order to transmit a signal with no error. Furthermore, in high-speed transmission, since the amplitude of a waveform is small, a design margin is small.
One of the design elements of high-speed transmission between LSIs is a termination resistor. This termination resistor is installed at both ends of a transmission path (transmission line) between LSIs. A termination resistor plays a role of improving the electrical characteristic of a transmission path by preventing the reflection of a transmission signal at both ends of the transmission path and preventing the waveform of a transmission signal from being disturbed. The disturbed waveform of a transmission signal deteriorates the high-speed transfer of a signal in high-speed transmission. It is necessary to keep the resistance value of a termination resistor constant as much as possible in such a way as to meet the regulations of a transmission path.
Recently, the negative influences on a transmission path of changes in the resistance value of a termination resistor have been tending to get greater and greater due to the low power consumption of an LSI (reduction of power voltage), the effects of high-speed transmission, improvement in chip integration, and the like. Therefore, the adjustment accuracy of a termination resistor has become an important factor for realizing high-speed transmission between LSIs.
FIG. 11 is a basic configuration of a transmission device for transmitting/receiving data between LSIs.
The transmission device 900 illustrated in FIG. 11 includes an LSI 1000 (LSIa), an LSI 2000 (LSIb), and transmission paths 3001 and 3002 between those LSIs. The LSIs 1000 and 2000 exchange data with each other via the transmission paths 3001 and 3002.
The LSI 1000 includes an output driver (transmitting driver) 1001, a receiver 1002, signal wires 1011 and 1012, and termination resistors 1021 and 1022. The signal wire 1011 connects between the transmitting driver 1001 and the transmission path 3001. The termination resistor 1021 is connected between the signal wire 1011 and the ground. The signal wire 1012 connects between the receiver 1002 and the transmission path 3002. The termination resistor 1022 is connected between the signal wire 1012 and the ground.
The LSI 2000 has the same configuration as the LSI 1000. The LSI 2000 includes a transmitting driver (output driver) 2001, a receiver 2002, signal wires 2011 and 2012, and termination resistors 2021 and 2022. The signal wire 2012 connects between the receiver 2002 and the transmission path 3001. The termination resistor 2022 is connected between the signal wire 2012 and the ground. The signal wire 2011 connects between the transmitting driver 2001 and the transmission path 3002. The termination resistor 2021 is connected between the signal wire 2011 and the ground.
In a transmission device 900 having the above configuration the characteristic impedance of the termination resistors 1021 and 2022 is adjusted in such a way as to meet the regulation value of a transmission path, taking into account the characteristic impedance of the transmission path 3001, and to match their impedance. Similarly, the characteristic impedance of the termination resistors 1022 and 2021 is adjusted in such a way as to meet the regulation value of a transmission path and to realize good high-speed transmission.
A technique for controlling so as to match termination resistance with the characteristic impedance of a transmission path as in the above transmission device 900 is disclosed by, for example, Japanese Laid-open Patent Publication Nos. 2003-122465 and 2001-175373 and the like.
FIGS. 12A and 12B are an example of the general configuration of a conventional inter-LSI transmission device.
The inter-LSI transmission device 4000 illustrated in FIGS. 12A and 12B includes two LSIs 4100 (LSIA) and 4200 (LSIB), and transmission paths (inter-LSI chip transmission paths) 4300 and 4400 connecting between those two LSIs 4100 and 4200. The LSIs 4100 and 4200 are connected by the two transmission paths 4300 and 4400. The transmission path 4300 is used for the LSI 4100 to transmit data to the LSI 4200 and the transmission path 4400 is used for the LSI 4200 to transmit data to the LSI 4100. The transmission path 4300 is composed of four signal wires 4301-1 through 4301-4 and the transmission path 4400 is composed of four signal wires 4401-1 through 4401-4.
The respective interface units of the LSIs 4100 and 4200 have the same circuit configuration. The interface unit of the LSI 4100 is the circuit of the LSI 4100, excluding a control unit 4110. The interface unit of the LSI 4200 is the circuit of the LSI 4200, excluding a control unit 4210.
Therefore, the circuit configuration of the LSI 4100 is mainly explained here and the explanation of the LSI 4200 is omitted.
The LSI 4100 includes a control unit 4110, a transmitting buffer 4120, a transmitting packet processing unit 4130, a data transmitting control unit 4140, a transmitting unit 4150, a receiving unit 4160, a received packet processing unit 4170, and a receiving buffer 4180.
The control unit 4110 generates/controls a packet transmitted to/received from a communication partner LSI and so on.
A packet generated/controlled by the control unit 4110 is, for example, a packet controlled by a transaction layer or the like. The control unit 4110 controls a packet to be transmitted to a communication partner LSI (transmitting packet) and stores the transmitting packet in the transmitting buffer 4120. The control unit 4110 extracts a packet received from a communication partner LSI (received packet), and so on from the receiving buffer 4180.
The transmitting buffer 4120 stores a transmitting packet from the control unit 4110. The position of the transmitting packet stored in the transmitting buffer 4120 (storage position) is structured to be controlled by a pointer controlled by the data transmitting control unit 4140.
The transmitting packet processing unit 4130 includes a transmitting data processing 1 unit 4130a and a CRC insertion unit 4130b. The transmitting data processing 1 unit 4130a extracts a transmitting packet from the transmitting buffer 4120 and outputs the packet to the CRC insertion unit 4130b. The CRC insertion unit 4130b generates the CRC code (cyclic redundancy check code) of the transmitting packet and inserts the CRC code into the transmitting packet. Then, the transmitting packet processing unit 4130 outputs the transmitting packet in which the CRC code is inserted to the transmitting unit 4150.
The transmitting unit 4150 includes a data processing 2· transfer unit 4150a, four transmitting drivers 4150b-1 through 4150b-4, termination resistors 4151-1 through 4151-4 connected between signal wires 4301-1 through 4301-4 connected to the output terminal of the transmitting driver and the ground, and a transmitting side termination resistor update control T unit 4150t. The data processing 2· transfer unit 4150a divides a transmitting packet received from the transmitting data processing unit 4130 into four pieces of data and outputs each piece of the data to each of the four transmitting drivers 4150b-1 through 4150b-4. Each of the transmitting drivers 4150b-1 through 4150b-4 outputs the data input from the data processing 2· transfer unit 4150a to each of the signal wires 4301-1 through 4301-4. The transmitting side termination resistor update control T unit 4150t is connected to a termination resistance adjustment circuit 4163, which will be described later. The transmitting side termination resistor update control T unit 4150t updates the resistance values of the termination resistors 4151-1 through 4151-4 to appropriate values on the basis of a control signal input from the termination resistance adjustment circuit 4163. These appropriate values are set by the resistance value of an external reference resistor Ra, which depends on an environmental change and is difficult to change.
The receiving unit 4160 includes a data processing 3· transfer unit 4160a, four receivers 4160b-1 through 4160b-4, termination resistors 4161-1 through 4161-4 connected between signal wires 4401-1 through 4401-4 connected to the input terminal of the receiver 4160b-1 through 4160b-4 and the ground, and a termination resistance adjustment circuit 4163. The data processing 3· transfer unit 4160a combines the four pieces of data input from each of the four receivers 4160b-1 through 4160b-4 to reproduce a packet and outputs the packet to the received packet processing unit 4170. The termination resistance adjustment circuit 4163 includes a resistance adjustment circuit 4163a and a receiving side update control unit 4163r. A reference resistor (external reference resistor) Ra externally installed in the LSI 4100 is connected to the termination resistance adjustment circuit 4163. The termination resistance adjustment circuit 4163a and the external reference resistor Ra are connected by the terminal (pin) of the LSI 4100 and the wiring connected to the terminal.
The external reference resistor Ra has a resistance value that becomes the base of the value (resistance value) of the termination resistors 4151-1 through 4151-4 and 4161-1 through 4161-4. By adjusting in such a way that the resistance values of the termination resistors 4151-1 through 4151-4 and 4161-1 through 4161-4 equal the resistance value of the external reference resistor Ra, impedance is adjusted at the terminal end of the transmission paths 4300 and 4400, and signal reflection at the terminal end of the transmission paths 4300 and 4400 is suppressed.
The resistance adjustment circuit 4163a of the termination resistance adjustment circuit 4163 generates a control signal for adjusting the resistance values of termination resistors 4151-1 through 4151-4 and 4161-1 through 4161-4, by referring to the resistance value of the external reference resistor Ra. The resistance values of the termination resistors 4151-1 through 4151-4 and 4161-1 through 4161-4 which change due to the influence of the change of ambient temperature, the fluctuation of power voltage, and the like are set to the adjusted resistance value. The receiving side update control T unit 4163r updates the resistance values of the termination resistors 4161-1 through 4161-4 in such a way that the resistance values of the termination resistors 4161-1 through 4161-4 equal the resistance value of the external reference resistor Ra on the basis of a control signal input from the resistance adjustment circuit 4163a. 
The resistance adjustment circuit 4163a of the receiving unit 4160 is connected to the transmitting side update control T unit 4150t of the transmitting unit 4150. When the power of the LSI 4100 is switched on, the resistance adjustment circuit 4163a sets the resistance values of both the termination resistors 4161-1 through 4161-4 of the receiving unit 4160 and the termination resistors 4151-1 through 4151-4 of the transmitting unit 4150 to the resistance value adjusted by referring to the resistance value of the external reference resistor Ra.
The received packet processing unit 4170 includes a received data processing unit 4170a and a CRC checker 4170b. The CRC checker 4170b applies a CRC check to data received from the receiving unit 4160 and notifies the data processing unit 4170a of the data of a packet and the like, error information, and the like. When determining from the notice from the CRC checker 4170b that the received packet has failed, the data processing unit 4170a notifies the transmitting packet processing unit 4130 of the failure of the received packet. The transmitting unit 4150 transmits a request for requesting the retransmission of the failed packet (retransmit request) to the receiving unit 4260 of the LSI 4200 via the transmission path 4300.
When receiving a report that the received packet has not failed from the CRC checker 4170b, the data processing unit 4170a removes the header of a lower-ordered layer (for example, a data link layer), CRC data or the like from the received packet, generates the received packet of a higher-ordered layer (for example, a transaction layer) and stores the generated received packet in the receiving buffer 4180.
The receiving buffer 4180 stores packets received from the received packet processing unit 4170. The received packets stored in the receiving buffer 4180 are read by the control unit 4110.
The LSI 4200 (LSIB) includes a control unit 4210, a transmitting buffer 4220, a transmitting packet processing unit 4230, a data transmitting control unit 4240, a transmitting unit 4250, a receiving unit 4260, a received packet processing unit 4270 and a receiving buffer 4280. The circuit configuration of the interface unit of the LSI 4200 is the same as that of the above-described LSI 4100 (LSIA). The same descriptions are attached to the same components in the LSI 4200 as those of the LSI 4100. A reference resistor (external reference resistor) Rb is externally installed in the termination resistance adjustment circuit 4263 of the LSI 4200.
The configurations of the termination resistance adjustment circuit 4163 of the LSI 4100 and the termination resistance adjustment circuit 4263 of the LSI 4200 are disclosed by, for example, Japanese Laid-open Patent Publication No. 2006-203405. The resistance adjustment circuits 4163a and 4263a of the termination resistance adjustment circuits 4163 and 4263 correspond to the calibration circuit disclosed by Japanese Laid-open Patent Publication No. 2006-203405.
The transmitting unit 4150 of the LSI 4100 and the receiving unit 4260 of the LSI 4200 are connected by the transmission path 4300. The transmitting unit 4250 of the LSI 4200 and the receiving unit 4160 of the LSI 4100 are connected by the transmission path 4400. The LSIs 4100 and 4200 can conduct both-way communications by using the transmission paths 4300 and 4400. More specifically, the transmitting drivers 4150b-1 through 4150b-4 of the transmitting unit 4150 of the LSI 4100 and the receivers 4260b-1 through 4260b-4 of the LSI 4200 are connected by the signal wires 4301-1 through 4301-4, respectively. The transmitting drivers 4250b-1 through 4250b-4 of the transmitting unit 4250 of the LSI 4200 and the receivers 4160b-1 through 4160b-4 of the LSI 4100 are connected by the signal wires 4401-1 through 4401-4, respectively. Therefore, in order for the LSI 4200 to accurately receive data from the LSI 4100, it is desired to adjust the resistance values of the termination resistors 4261-1 through 4261-4 of the receiving unit 4260 of the LSI 4200 to desired resistance values via the resistance value of the external reference resistor Rb. On the other hand, it is desired to adjust the resistance values of the termination resistors 4151-1 through 4151-4 of the transmitting unit 4150 of the LSI 4100 to a desired resistance values via the resistance value of the external reference resistor Ra. Similarly, in order for the LSI 4100 to accurately receive data from the LSI 4200, it is desired to adjust the resistance values of the termination resistors 4161-1 through 4161-4 of the receiving unit 4160 of the LSI 4100 to desired resistance values via the resistance value of the external reference resistor Ra, and the resistance values of the termination resistors 4251-1 through 4251-4 of the transmitting unit 4250 of the LSI 4200 to desired resistance values via the external reference resistor Rb.
The operation in the case where the LSI 4100 transmits data to the LSI 4200 will be briefly explained below. A packet transferred from the control unit 4110 of the LSI 4100 is transferred to the data processing 1 unit 4130a of the transmitting packet processing unit 4130 via the transmitting buffer 4120 of the LSI 4100. The CRC insertion unit 4130b of the transmitting packet processing unit 4130 generates the CRC code of the packet input to the data processing 1 unit 4130a. The transmitting packet processing unit 4130 inserts the CRC code generated by the CRC insertion unit 4130b in the packet input by the data processing 1 unit 4130a and outputs the packet in which the CRC code is inserted to the transmitting unit 4150. The transmitting unit 4150 transmits the packet received from the transmitting packet processing unit 4130 to the transmission path 4300. The receiving unit 4260 of the LSI 4200 receives the packet transmitted via the transmission path 4300. The receiving unit 4260 transfers the packet transmitted from the LSI 4100 to the data processing 4 unit 4270a of the received packet processing unit 4270. The CRC checker 4270b of the received packet processing unit 4270 applies a data error check using a CRC to the packet (received packet) that the data processing 4 unit 4270a has received from the receiving unit 4260.
The CRC checker 4270b notifies the data processing 4 unit 4270a of the detection result of the data error of the received packet. If there is no error in the received packet, the data processing 4 unit 4270a writes the received packet in the receiving buffer 4280. If there is any error in the received packet, the data processing unit 4270a notifies the transmitting packet processing unit 4230 of error information about the packet whose error is received. Upon receipt of the error information from the received packet processing unit 4270, the transmitting packet processing unit 4230 generates a retransmit request and transmits the request to the transmitting unit 4250. The transmitting unit 4250 transmits the retransmit request received from the transmitting packet processing unit 4230 to the transmission path 4400.
The receiving unit 4160 of the LSI 4100 receives the retransmit request transmitted by the LSI 4200 via the transmission path 4400. The receiving unit 4160 transfers the retransmit request received from the LSI 4200 to the received packet processing unit 4170. Upon receipt of the retransmit request from the receiving unit 4160, the received packet processing unit 4170 requests that the LSI 4200 retransmit the packet whose error is received by notifying the data transmitting control unit 4140 of information about the packet whose error the LSI 4200 has received. The data transmitting control unit 4140 puts the pointer of the transmitting buffer 4120 back up to the storage position of a packet to be retransmitted. The transmitting packet processing unit 4130 reads the packet indicated by the pointer from the transmitting buffer 4120 and transfers the packet whose error is received by the LSI 4200 to the transmitting unit 4150. The transmitting unit 4150 transmits the packet received from the transmitting packet processing unit 4130 to the LSI 4200 via the transmission path 4300. Thus, a packet whose error is received by the LSI 4200 is retransmitted from the LSI 4100 to the LSI 4200.
When normally receiving a packet from the LSI 4100, the LSI 4200 notifies the LSI 4100 of the normal reception of the packet. When the LSI 4100 has received from the LSI 4200 the notice on the normal reception of the packet, the data transmitting control unit 4140 recognizes the normal reception of the packet and reflects it in the control of the pointer. Then, the data transmitting control unit 4140 continues to transmit packets to the LSI 4100.
Japanese Laid-open Patent Publication No. 2003-122465 discloses a technique for detecting the stoppage of data transmission/reception and correcting a termination resistance when the data transmission/reception is stopped. Japanese Laid-open Patent Publication No. 2001-175373 discloses a communication device provided with a dummy load means which can keep the impedance of a transmission line always equal to that of a termination resistor means.
The value (resistance value) of a termination resistor varies depending on the temperature of its ambient environment (for example, the temperature of an LSI chip) and the like. A computer system is often continuously operated for a long time. When the operation time becomes long, the temperature inside a device rises accordingly. Therefore, when a computer system is consecutively operated, the temperature of a semi-conductor device mounted on the computer system rises due to the heat of itself and its surroundings. Therefore, when a computer system is often consecutively operated for a long time, the resistance value of a termination resistor installed inside a semi-conductor device mounted on the computer system changes. Thus, in a high-speed transmission between LSIs in a computer system, a signal waveform to be transmitted is distorted by their impedance mis-matching and an error occurs in received data.
To cope with the above-described temperature change of a computer system, when a computer system is consecutively operated for a long time, it is desired to control in such a way that the resistance values of termination resistors installed at both ends of a transmission path between LSIs may always become optimal. However, when the resistance value of a termination resistor is modified within data transfer, sometimes data which can be normally transmitted without such a modification cannot be normally received. Therefore, it is desired to adjust the resistance value of a termination resistor in such a way that no error may be caused in data transfer.